https://strike.scec.org/scecwiki/index.php?action=history&feed=atom&title=Comparison_of_Compute_Nodes 2026-04-29T00:44:51Z Revision history for this page on the wiki MediaWiki 1.34.2 https://strike.scec.org/scecwiki/index.php?title=Comparison_of_Compute_Nodes&diff=13553&oldid=prev 2015-06-25T19:48:05Z

<p>Created page with &#039; == Option 1 == Option 1: Nvidia GPU – strength is in processing power (flops) and memory bandwidth. *Pros: ** Ideal for multi threaded/parallel and floating point code ** C…&#039;</p> <p><b>New page</b></p><div><br /> == Option 1 ==<br /> Option 1: Nvidia GPU – strength is in processing power (flops) and memory bandwidth. <br /> <br /> *Pros:<br /> ** Ideal for multi threaded/parallel and floating point code<br /> ** CUDA programming allows for control over memory hierarchy, data movement and synchronization<br /> ** 3rd party software applications have CUDA hooks available, so users just have to activate. Matlab, R<br /> ** Standard compilers and parallel programming models can take advantage of GPUS<br /> ** Still requires x86 chipset so nodes with GPUs still can be utilized by jobs running x86<br /> **Well documented, tutorials and courses available on the web<br /> <br /> *Cons:<br /> ** Not efficient for graph algorithms, sparse linear algebra, searches and sorts<br /> ** Need to learn CUDA programming language to take full advantage of GPU or code could actually run slower than x86 chipset<br /> ** Programmers must think about best use of memory on device and data transfers<br /> ** Requires increased power and cooling<br /> <br /> == Option 2 ==<br /> Option 2: Intel Xeon PHI<br /> <br /> *Pros:<br /> ** Potentially a simple recompile will enable PHI <br /> ** Standard compilers and parallel programming models can take advantage of PHI<br /> ** Coding for PHI is similar to standard x86 coding – porting relatively straightforward (according to TACC)<br /> ** Still requires x86 chipset so nodes with accelerators still can be utilized by jobs running x86<br /> ** Wider vector unit, wider hardware thread count<br /> ** TACC (Texas Advanced Computing Center) has large PHI center and provide documentation and are collaborative<br /> ** Code optimized for PHI should also result in optimized CPU utilization<br /> <br /> *Cons:<br /> ** Typically need to learn PHI programming to properly take advantage of PHI or code could actually run slower than x86 chipset<br /> ** Programmers must think about best use of memory on device and data transfers – performance requires effort<br /> ** Has three runtime modes – PHI, MPI on host and PHI, MPI on host offload to PHI – administratively challenging, end-user <br /> ** Co processor runs a stripped down linux operating system requiring administrative overhead to seamlessly provide compute job access, data, applications and user code<br /> ** Intel is re-designing PHI and will be releasing new architected version sometime in Q# 201#<br /> ** Requires increased power and cooling<br /> <br /> == Option 3 ==<br /> Option 3: No accelerator – use X86 Chipset<br /> <br /> *Pros:<br /> ** General purpose and already implemented by applications and general code<br /> ** No additional costs so can obtain more x86 nodes with same budget<br /> ** No additional power or cooling requirements so potentially more nodes in for existing infrastructure footprint<br /> <br /> *Cons:<br /> ** Cutting edge technology not available for researchers to take advantage<br /> ** No scaling up testbed available for national centers which utilize accelerators for larger multi processor jobs<br /> <br /> == Related Links ==<br /> *[[CME Project]]<br /> *[[Main Page]]</div>

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